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? semiconductor components industries, llc, 2013 july, 2013 ? rev. 3 1 publication order number: NCP5269/d NCP5269 synchronous buck controller with auto power saving mode and 2-bit vid inputs for system agent NCP5269 is a synchronous buck controller that is optimized for converting the battery voltage or adaptor voltage into power supply rails required in notebook and desktop system. NCP5269 is designed for applications requiring dynamically selected slew ? rate controlled output voltages. the soft ? start is programmed by a single capacitor. voltage identification logic ? inputs select four resistor programmed set ? point reference voltages that directly set the output voltage of the converter between 0.65 v to 1.5 v. NCP5269 supports high ef ficiency, fast transient response and provides power good signal. on semiconductor proprietary adaptive ? ripple control enables seamless transition from ccm to dcm, where converter runs at reduced switching frequency with much higher efficiency. the part operates with input voltage ranging from 3.3 v to 28 v. NCP5269 is available in a 20 ? pin 3 mm x 3 mm qfn package. features ? wide input voltage range: from 3.3 v to 28 v ? three selectable fixed frequency 300 khz, 400 khz or 600 khz ? 2 ? bit vid selects four independent voltages from 0 . 65 v to 1.5 v ? 1.0% system accuracy ? differential remote output voltage sensing ? soft transient control reduces inrush current and audio noise ? build ? in power ? good masking supports voltage identification (vid) on ? the ? fly transients ? simple resistor programming voltage levels ? programmable soft ? start through a single capacitor ? automatic power ? saving mode ? input supply voltage feed forward control ? resistive or lossless inductor?s dcr current sensing ? over ? temperature protection ? built ? in adaptive gate drivers ? output discharge operation ? built ? in over ? voltage, under ? voltage and over ? current protection and power good output ? this is a pb ? free device applications ? notebooks, desktops & servers ? i/o supplies ? system power supplies ? graphic cards 20 pin qfn, 3x3 mn suffix case 485bc device package shipping ? ordering information NCP5269mntwg qfn20 (pb ? free) 3000 / tape & reel marking diagram 5269 = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. pin connections (top view) (note: microdot may be in either location) 5269 alyw bst gh swn vccp gl/fset en vcc vid1 vid0 v3 comp fb fbrtn csn csp v2 v1 vref pg pgnd agnd 1
NCP5269 http://onsemi.com 2 figure 1. block diagram v1 vref + ? csp csn csa gh gl/fset vccp bst pgnd sw control logic ramp generator and pwm logic uvlo, uvp, ovp, power good ocp, tsd and protection + ? e/a comp fb internal reference oc & tre detection en pg agnd v2 v3 vid decoder & vref selection vid1 vid0 precision reference fbrtn vcc + ?
NCP5269 http://onsemi.com 3 table 1. pin descriptions pin no. symbol description 1 en logic control for enabling the switcher. applying greater than 1.4 v will turn on the part. connect to gnd to disable. 2 vcc supply for analog circuit. 3 vid1 logic input for reference voltage selector. use in conjunction with the vid0 pin to select among four set ? point reference voltages. 4 vid0 logic input for reference voltage selector. use in conjunction with the vid1 pin to select among four set ? point reference voltages. 5 v3 voltage set ? point programming resistor input. 6 v2 voltage set ? point programming resistor input. 7 v1 voltage set ? point programming resistor input. external reference input when enabled by connecting the v3 pin to the vcc pin. 8 vref soft ? start programming capacitor input. set - point reference voltage programming resistor input. connects internally to the inverting input of the vset voltage set - point amplifier. 9 pg power good indicator of the output voltage. open ? drain output. 10 pgnd ground reference and high ? current return path for the bottom gate driver. 11 gl/fset gate driver output of bottom n ? channel mosfet. and it is also used to set up switching frequency by connecting a resistor from this pin to ground. 12 vccp power supply for mosfet gate drive 13 swn switch node between the top mosfet and bottom mosfet. 14 gh gate driver output of the top n ? channel mosfet. 15 bst top gate driver input supply, a bootstrap capacitor connection between swn and this pin. 16 csp inductor current differential sense non ? inverting input. 17 csn inductor current differential sense inverting input. 18 fbrtn feedback return input/output. this pin remotely senses the output voltage. it is also used as the ground return for the vid reference voltage and the voltage error amplifier blocks. 19 fb output voltage feed back. 20 comp output of the error amplifier. agnd analog ground. bottom thermal pad.
NCP5269 http://onsemi.com 4 7 6 9 8 10 11 12 13 14 15 5 4 3 2 1 19 20 17 18 16 csp csn comp fb pg pgnd gh bst v1 v2 v3 agnd fbrtn vin cin lo cout vout r1 r2 c2 c1 c3 en vcc 5.0 v vid1 vid0 pg vcc rset1 rset2 rset3 rset4 v ccp 5.0v fbrtn r3 r4 fbrtn figure 2. application circuit c vccp c boot c ss vref swn vccp gl/fset table 2. absolute maximum ratings rating value vcc to agnd ? 0.3 v (dc) to 6.5 v fbrtn, pgnd ? 0.3 v to +0.3 v swn to pgnd ? 5.0 v to 28 v, ? 10.0 v for t < 100 ns bst, gh to gnd ? 0.3 v to 34 v bst to swn, gh to swn, vcc to pgnd, dl to pgnd ? 0.3 v to 6.5 v all other pins ? 0.3 v to 6.5 v operating temperature range, t a ? 40 c to +100 c junction temperature, t j ? 40 c to +100 c storage temperature range, t s ? 55 c to +150 c package characteristic thermal resistance from junction ? to ? ambient (t a = +25 c), r thja 35 c/w (note 1) stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this data is for solder on 4 ? layer board with 2 oz. copper.
NCP5269 http://onsemi.com 5 table 3. electrical characteristics (v cc = v ccp = 5.0 v, v out = 1.0 v, t a = +25 c for typical value; ? 40 c < t a < 100 c for min/max values unless noted otherwise) parameter symbol test conditions min typ max units power supply vcc operation voltage v cc 4.5 5 5.5 v vccp operation voltage v ccp 4.5 5 5.5 v voltage monitoring & protection vcc start threshold 3.9 4.2 4.45 v vcc uvlo hysteresis 300 350 400 mv power good low voltage i pg(sink) = 4 ma 230 300 mv power good high leakage current 1.0 a power good startup delay (note 2) measure from ssend to pg pos edge 3.3 ms power good propagation delay delay for power good in 3.3 ms delay for power good out 1.5 s power good threshold power good in from high 101.5 105 107.5 % power good in from low 92.5 95 98.5 % pg hysteresis 5 % power good masking time triggered by any vid change 425 s fb overvoltage threshold v ovfb ? vid relative to nominal vid voltage 150 200 250 mv overvoltage propagation delay 1.5 s fb over voltage threshold during soft ? start 2.0 v fb under ? voltage trip threshold v uvfb ? vid relative to nominal vid voltage ? 360 ? 300 ? 240 mv undervoltage protection blanking time 3.3 s supply current vcc quiescent current i vcc v skip = 0 v, v fb = 1.5 v, en = 5.0 (no switching), gh and gl are open 3.9 5 ma vcc shutdown supply current i vcc_sd en = 0 v 3 a vccp quiescent current i vccp v skip = 0 v, v fb = 1.5 v, en = 5.0 (no switching), gh and gl are open 0.3 ma vccp shutdown supply current i vccp_sd en = 0 v 1 a bst quiescent current i bst v skip = 0 v, v fb = 1.5 v, en = 5.0 (no switching), gh and gl are open 0.33 ma bst shutdown supply current i bst_sd en = 0, bst = 5 v, swn = 0 1 a feedback voltage reference voltage v ref 0. 65 v system accuracy vid0 = vid1 = high, pwm in ccm mode, ? 40 c < t a < 100 c ? 1.0 +1.0 % t a = 25 c ? 0.35 +0.35 % feedback voltage line regulation vcc = 4.5 v ~ 5.5 v 0.75 %/v 2. guaranteed by characterization or correlation, not production tested
NCP5269 http://onsemi.com 6 table 3. electrical characteristics (v cc = v ccp = 5.0 v, v out = 1.0 v, t a = +25 c for typical value; ? 40 c < t a < 100 c for min/max values unless noted otherwise) parameter units max typ min test conditions symbol voltage error amplifier open loop dc gain (note 2) 80 db open loop unity gain bandwidth (note 2) f 0db,ea 20 mhz fb input voltage range (note 2) 0 2.0 v fb bias current (note 2) relative to csn = vid ? 1 1 a slew rate comp pin to gnd = 10 pf 10 v/ s maximum output voltage 10 mv of overdrive, i source = 2.0 ma 3.3 3.5 v minimum output voltage 10 mv of overdrive, i sink = 2.0 ma 0.2 0.3 v output source current 10 mv of overdrive, v out = 3.5 v 2 m a output sink current 10 mv of overdrive, v out = 1.0 v 2 m a differential current sense amplifier csp and csn common ? mode input voltage range refer to agnd ? 0.2 2.0 v differential input voltage range ? 30 30 mv over current protection ocp threshold v(csp) ? v(csn), vo = 1 v vo = 0.5 v ~ 1.5 v 27 26 30 30 33 34 mv 2_bits vid vid0, vid1 high threshold voltage 0.65 v vid0, vid1 low threshold voltage 0.4 v vid0, vid1 input bias current vid = 0 v 1 na vid0, vid1 pull down current 2.5 a charging current during vid up (note 2) 73 a discharging current during vid down (note 2) 90 a vid delay time any vid edge to 10% of fb change 200 ns en en high threshold voltage 1.4 v en low threshold voltage 0.4 v en input bias current i en en = 5 v 10 a en input voltage 5.5 v pwm minimum controllable on time (note 2) 30 ns minimum off time (note 2) 300 400 500 ns pwm ramp amplitude (note 2) v in = 5 v 1.25 v v in = 12 v 3 v 2. guaranteed by characterization or correlation, not production tested
NCP5269 http://onsemi.com 7 table 3. electrical characteristics (v cc = v ccp = 5.0 v, v out = 1.0 v, t a = +25 c for typical value; ? 40 c < t a < 100 c for min/max values unless noted otherwise) parameter units max typ min test conditions symbol internal bst diode forward voltage drop i f = 10 ma, t a = 25 c 0.3 v reverse ? bias leakage current v bst = 34 v, v sw = 28 v, t a = 25 c 0.1 1 a soft stop output discharge on ? resistance en = 0, v out = 0.65 v 14 30 discharge threshold in vcc 0.6 v soft start soft start current i ss 20 a oscillator oscillator frequency f sw r set = 2k 270 300 330 khz oscillator frequency accuracy 10 % gate driver gh pull ? high resistance (note 2) rh_gh source, v(bst ? gh) = 0.1 1.3 1.8 gh pull ? low resistance (note 2) rl_gh sink, v(gh ? swn) = 0.1 v 1.1 1.6 gl pull ? high resistance (note 2) rh_gl source, v(vcc ? gl) = 0.1 v 1.0 1.8 gl pull ? low resistance (note 2) rl_gl sink, v(gl ? pgnd) = 0.1 v 0.5 0.9 gh source current 2 a gh sink current 2 a gl source current 2 a gl sink current 4 a dead time gl off to gh on 10 20 30 ns gh off to gl on 10 20 30 thermal shutdown thermal shutdown threshold (note 2) 150 c thermal shutdown hysteresis (note 2) 25 c 2. guaranteed by characterization or correlation, not production tested
NCP5269 http://onsemi.com 8 detailed description overview NCP5269 is designed for applications requiring dynamically selected slew ? rate controlled output voltages. it provides a synchronous pwm controller that incorporates all the control and protection circuitry necessary to satisfy a wide range of applications. the NCP5269 pwm controller employs adaptive ripple control to provide seamless transition between ccm and dcm while maintain high efficiency during light load. it also provides fast transient response and excellent stability. the features of the NCP5269 include a 2 bits vid selectable and external programmable reference, fixed three preset switching frequency, an error amplifier, adaptive gate driver, programmable soft ? start, and very low shutdown current. the protection features of the NCP5269 include over ? current protection, power good monitor, over voltage and under voltage protection, built in output discharge and thermal shutdown. reference voltage programming the NCP5269 incorporates 2 ? bits vid, which selects four user ? programmed reference voltages that reflect on vref pin. NCP5269 measures vfb and vref pin voltage relative to fbrtn pin. an internal reference that allows output voltages as low as 0.65 v. the tolerance of the internal reference is guaranteed over the entire operating temperature range of the controller. the reference voltage is trimmed using a test configuration that accounts for error amplifier offset and bias currents. the vid truth tables for each part are listed below. table 4. NCP5269 vid truth table vid state results vid0 vid1 close v ref v out 0 0 sw3 vset3 v out4 0 1 sw2 vset2 v out3 1 0 sw1 vset1 v out2 1 1 sw0 vset0 v out1 ? + e/a fb comp + ? vset ref 650 mv v1 v2 v3 sw0 sw1 sw2 sw3 r3 r4 r5 r6 fbrtn css fbrtn r1 r2 fbrtn v ref v out figure 3. external reference voltage and output voltage setting vset0, vset 1 , vset 2 and vset 3 can be calculated based on the following equations: v set0 v inref v set1 v inref 1 r 3 r 4 r 5 r 6 v set2 v inref 1 r 3 r 4 r 5 r 6 v set3 v inref 1 r 3 r 4 r 5 r 6 and v set3 v set2 v set1 v set0 vset0, vset 1 , vset 2 and vset 3 are in the range of 0 . 65 v~1 . 5 v. if the required output voltage is higher than 0.65 v~1.5 v, a feedback voltage divider (a resistor r2 is added from fb pin to fbrtn) can be used to boost the output voltage up. so the output voltage can be calculated based on the following equations: v out1 v set0 1 r 1 r 2 and v out4 v out3 v out2 v out1 v out2 v set1 1 r 1 r 2 v out3 v set2 1 r 1 r 2 v out4 v set3 1 r 1 r 2
NCP5269 http://onsemi.com 9 external reference voltage NCP5269 accepts external reference voltage. to enable this feature, tie v3 to vcc and feed v1 from external reference. then internal 650 mv reference is replaced by the voltage on v1 pin. the output voltage is programmed by resistor hooked from fb to fbrtn. vid0 and vid1 are disabled with this function. please ground both vid0 and vid1 pins. all the resistors on vref, v1, v2 and v3 are removed. the soft ? start cap c ss remains on the vref pin. the v2 pin can be left open. the reference voltage on v1 pin can be from 0.5 v to 2.0 v. however, the NCP5269 does not provide soft ? transient feature, forced ccm operation and pg blanking for any reference voltage jump on v1. therefore, external slewrate control or r/c is recommended to soften the reference voltage change on v1 pin input. in addition, minimum load current is required to discharge the output voltage when the reference voltage on v1 pin moves lower, in order to avoid false pg failure. for example, 1 ma minimum load current is needed to discharge the output voltage, given 0.5 mf output capacitance and external r = 10 k , c = 1 f on the v1 pin to slow down the reference voltage change. the minimum load current requirement is proportional to the output capacitance and v1 pin reference voltage slewrate. the initial reference voltage on v1 pin should be established prior to en assertion. differential sensing of output voltage the NCP5269 combines differential sensing with a high accuracy vid dac, referenced by a precision band gap source and a low offset error amplifier, to provide accurate output voltage. the output voltage is sensed between the fb and fbrtn pins. fb should be connected through a resistor to the positive regulation point. fbrtn should be connected directly to the negative remote sensing point. external soft ? start and vid change slew rate to limit the start ? up inrush current, a capacitor can be connected from vref pin to ground to ramp up reference voltage slowly. during this period, the set amplifier output 20 a current to char ge capacitor c ss . the soft start period can be calculated by the following equation: t ss ? r a c ss ln 1 v o i sa1 r a where: ? ra is the sum of the series resistors from vref to ground. r a = r 3 + r 4 + r 5 + r 6 ? i sa1 is soft start current 20 a. ? vo is the initial output voltage set by vid the output current of the set amplifier will change to +73 a / ? 9 0 a after soft start period . so during voltage steps due to vid bit change, the slew rate of output voltage can be calculated as follows: t sl ? r a c ss ln 1 v o2 v o1 i sa2 r a where: ? i sa2 is the source/sink current limit of set amplifier during vid changing, which is 73/90 a . ? vo1 and vo2 are the voltages selected by vid inputs oscillator frequency a fixed precision oscillator is provided. the actual switching frequency is set at 300 khz, 400 khz or 600 khz by the resistor on gl/fset pin. the resistor and frequency can be referred to the table below. gl/fset resistor 2k 6k 15k switching frequency 300 khz 400 khz 600 khz error amplifier the error amplifier?s primary function is to regulate the converter?s output voltage, as shown in the applications schematic. a type iii compensation network must be connected around the error amplifier to stabilize the converter . it has a bandwidth of greater than 15 mhz, with open loop gain of at least 80 db. the comp output voltage is clamped to a level above the oscillator ramp in order to improve large ? scale transient response. soft stop soft ? stop or discharge mode is always on during faults or disable. in this mode, a fault (uvp, ovp, ocp, tsd) or disable (en) causes the output to be discharged through an internal 20 ? ohm transistor inside of vo terminal. the time constant of soft ? stop is a function of output capacitance and the resistance of the discharge transistor. adaptive non ? overlap gate driver in a synchronous buck converter, a certain dead time is required between the low side drive signal and high side drive signal to avoid shoot through. during the dead time, the body diode of the low side fet free - wheels the current. the body diode has much higher voltage drop than that of the mosfet, which reduces the efficiency significantly. the longer the body diode conducts, the lower the efficiency. NCP5269 implements adaptive dead time control to minimize the dead time, as well as preventing shoot through from happening. automatic power saving mode if the load current decreases, the converter will enter power save mode operation. during power save mode, the converter skips switching and operates with reduced frequency , which minimizes the quiescent current and maintains high efficiency. protections under voltage lockout (uvlo) there is under - voltage lock out protections (uvlo) for vcc in NCP5269, which has a typical trip threshold voltage 4.2 v and trip hysteresis 300 mv. if uvlo is triggered, the device resets and waits for the voltage to rise up over the
NCP5269 http://onsemi.com 10 threshold voltage and restart the part. please note this protection function does not trigger the fault counter to latch off the part. over voltage protection (ovp) when vfb voltage is 200 mv (typical) above v ref voltage for over 1.5 s blanking time, an ov fault is set. at that moment, the top gate driver is turned off and the bottom gate driver is turned on trying to discharge the output. the bottom gate driver will be turned off when vfb drops below under voltage threshold. en resets or power recycle the device can exit the fault. ovp is disabled during vid changes. under voltage protection (uvp) an uvp circuit monitors the vfb voltage to detect under voltage event. the under voltage limit is 300 mv (typical) below v ref voltage. if the vfb voltage is below this threshold over 3.3 s, an uv fault is set and the device is latched off such that both top and bottom gate drives are off. en resets or power recycle the device can exit the fault. uvp is delayed for soft start after en goes high. uvp is disabled during vid changes. power good monitor (pg) NCP5269 provides window comparator to monitor the fb voltage. the target voltage window and transition delay times of the pgood comparator are 5% (typ . ) and 3.3 ? ms delay for assertion (low to high), and 10% (typ) and 1.5 ? s delay for de ? assertion (high to low) during running. the pg pin is open drain 5 ? ma pull down output. during startup, pg stays low until the feedback voltage is within the specified range for about 3.3 ms. to prevent a false alarm; the power ? good circuit is masked during any vid change. the duration of the pg mask is set to approximately 425 s by an internal timer. over current protection (ocp) the NCP5269 protects converter if over ? current occurs. the current through inductor is continuously monitored with differential current sense. current limit threshold vth_oc between cs+ and cs ? is internally fixed to 30 mv. the current limit can be programmed by inductor?s dcr and current sensing resistor divider with rs1 and rs2. the rs1, rs2 and c can be calculated as: c r s1 r s2 l dcr the inductor peak current limit is: i lim(peak) v th_dc k dcr ,wherek r s2 r s1 r s2 the dc current limit is: i lim i lim(peak) v o v in v o 2 v in f sw l where vin is the input supply voltage of the power stage, and fsw is normal switching frequency. dcr l rs1 rs2 c vin vout vc + ? figure 4. inductor dcr current sensing circuit figure 5 shows ntc resistor network to compensate the temperature drift of dcr. dcr l r r1 rntc c r2 vin vout vc + ? figure 5. inductor dcr current sensing circuit with temperature compensation network r the if inductor current exceeds the current threshold, the high ? side gate driver will be turned off cycle ? by ? cycle. in the mean time, an internal oc fault timer will be triggered. if the fault still exists after about 8 clock cycles, the part latches off, both the high ? side mosfet and the low ? side mosfet are turned off. the fault remains set until the system has shutdown and re ? applied vcc and/or the enable signal en is toggled. pre ? bias startup in some applications the controller will be required to start switching when its output capacitors are charged anywhere from slightly above 0 v to just below the regulation voltage. this situation occurs for a number of reasons: the converter?s output capacitors may have residual charge on them or the converter?s output may be held up by a low current standby power supply. NCP5269 supports pre ? bias start up by holding low side fets off till soft start ramp reaches the fb pin voltage. thermal shutdown the NCP5269 protects itself from over heating with an internal thermal monitoring circuit. if the junction temperature exceeds the thermal shutdown threshold, an internal resistor will discharge vref and the voltage at the comp pin will be pulled to gnd, and both the upper and lower mosfets will be shut off. when temperature drops below threshold, the part will auto restart with soft ? start feature.
NCP5269 http://onsemi.com 11 package dimensions qfn20 3x3, 0.4p case 485bc issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. c seating plane d e 0.10 c a3 a a1 2x 2x 0.10 c dim a min max millimeters 0.80 1.00 a1 --- 0.05 a3 0.20 ref b 0.15 0.25 d 3.00 bsc d2 1.70 1.90 e 3.00 bsc 1.70 1.90 e2 e 0.40 bsc pin one reference 0.05 c 0.05 c note 4 a 0.07 c note 3 l e d2 e2 b b 6 16 20x 1 11 20x 0.05 c 0.20 0.40 l *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 3.30 1.86 0.40 0.52 20x 0.26 20x dimensions: millimeters top view side view bottom view b pitch 2x 2x l1 detail a l alternate terminal constructions ?? ?? 1 0.00 0.15 l1 k 0.30 ref k 20x on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCP5269/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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